The present invention relates to digital ADDER circuitry and more particularly to an improvement in the "Manchester Carry Chain."
In the addition of any two numbers, A and B the sum S.sub.k of the k.sup.th significant digit is dependent upon the value of the k.sub.th digits A.sub.k and B.sub.k and also upon the "carry" from the (k-1)th digit. Nominally when adding two N digit numbers time must be provided for the "carry" indication to propagate from the least significant bit position to the most significant bit position. Because the numbers used in performing digital addition electronically have only two values, "1" or "0", the propagation time of the "carry" indication can be foreshortened by using what has become known as the "Manchester Carry Chain." This circuitry is described in the article "Parallel Addition In Digital Computers: A New Fast Carry Circuit" described by T. Kilburn et al, Proc. IEE, Vol. 106, Pt.B, at pages 464-466. Foreshortening the "carry" propagation time decreases the total time required to add the two N digit numbers.
The basic "Manchester Carry Chain" comprises N-1 cascaded groups of switches for an N bit ADDER, and logic circuitry responsive to the N addend digits to control the switches. Each group of switches includes a series switch connected between the "carry" output of the next most least significant bit (digit) position and the "carry" input of the next most more significant bit position. In addition, a second switch is connected between the "carry" output of the immediate bit position and the logical "1" supply potential and a third switch is connected between the "carry" output of the immediate bit position and the logical "0" supply potential. Depending on whether the input values for the particular bit position are 11 or 00, the second or third switches will be closed respectively. On the other hand, if the bit values are 01 or 10 the series switch will be closed to propagate the "carry" signal from the next most least significant bit position.
A little reflection will convince the reader that if the kth digits A.sub.k and B.sub.k are both "0" or both "1" the kth carryout will be "0" and "1" respectively, regardless of the (k-1)th carryout. On the other hand, if the A.sub.k and B.sub.k values are 10 or 01 the kth carry output will be equal to the (k-1)th carry output which in the Manchester arrangement is passed by the series switch. The carry switching control logic will respond to the addends faster than the summing logic, thus the carry indication is made available to the more significant ADDER digit position in much less time than if it were necessary to complete the sum and carry of each least significant bit position before adding the values of the next bit position.
Typically, ADDER circuits are constructed in integrated circuit form, in which case the switches of a Manchester carry chain are realized with the principal conduction paths of transistors. The switch control circuits are designed with combinatorial logic gates, e.g., an AND gate and a NOR gate each responsive to the A.sub.k and B.sub.k values for controlling the second and third switches, respectively. The series switch is nominally controlled by the output of a half adder responsive to the A.sub.k and B.sub.k values.